CALL FOR PAPERS 1st Workshop on VERIFICATION AND DEBUGGING Associated with CAV 2006
Knowing that a design violates its specification is only the first step towards a correct system. The violation may be caused by a fault in the design, but also by an error in the specification or in the environment constraints. A designer needs to understand the violation and to locate and correct the fault that causes it.
Industrial experience shows that fault localization and rectification take much more time, effort, and expense than fault detection. Also, debugging often takes place late in the design cycle, which makes it a high-risk activity that may, if not done quickly and correctly, delay the release of a product.
The workshop addresses the technologies and methodologies that need to be employed after verification has detected the presence of a bug. It aims to combine the efforts of the computer-aided verification and software engineering communities, attracting work in the areas of algorithms, tools, and methodologies for failure analysis. We welcome submissions addressing debugging of software, circuit designs, or combinations of the two.
Topics of interest include
* explanation and simplification of error traces, * fault localization, * rectification of the design, the specification, or the environment description, * test case generation for debugging, * debugging techniques, * methodologies that facilitate debugging, * overviews that provide a novel view of the state of the art and stimulate discussion and further research, and * empirical studies on debugging.
Papers should contain original research, and sufficient detail to assess the merits and relevance of the contribution. For papers reporting experimental results, authors are strongly encouraged to make their data available with their submission. Simultaneous submission to other conferences with proceedings or submission of material that has already been published elsewhere is not allowed.
Important Dates
* Paper submission deadline: 24 April 2006 * Notice of acceptance/rejection: 22 May 2006 * Final version due: 19 June 2006 * CAV conference: 16-21 August
The 2006 conference on Computer-Aided Verification will be a part of the Federated Logic Conference in Seattle. The workshop will be held right before or right after CAV.
Further info
Details of the submission process, the date of the workshop, and the way in which the accepted papers will be published will be made available at http://www.ist.tugraz.at/vandd.html. The program committee can be reached at vandd2006(a)ist.tu-graz.ac.at.
For further info on FLOC, see http://research.microsoft.com/floc06/.
Program Committee
Roderick Bloem (Graz University of Technology), Alex Groce (Laboratory for Reliable Software, Jet Propulsion Laboratory), John Moondanos (Future Formal Technologies Group, Logic Design Group, Intel), Marco Roveri (ITC-irst), Fabio Somenzi (University of Colorado at Boulder), Markus Stumptner (University of South Australia), and Andreas Zeller (University of Saarbruecken).
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